1. Field of the Invention
The present invention relates to a digital receiver such as a FM multiplex broadcast receiver used for Frequency Modulation (FM) multiplex broadcasting, and more particularly to a digital receiver for receiving a digital modulated signal which is modulated in a digital form using a digital modulation section, for demodulating the digital modulated signal to a data signal by a demodulation section, and for performing desired processes on the data signal.
2. Description of the Prior Art
FIG. 40 is a configuration diagram showing a configuration of a conventional Frequency Modulation (FM) multiplex broadcast receiver as a digital receiver for receiving a digital modulated signal used for FM broadcasting and for displaying the received data.
In FIG. 40, reference numbers 1 and 2 designate antennas for receiving electromagnetic waves propagating in space, reference number 3 denotes a diversity section for selecting one of the antennas based on a control signal (sig7a) transferred from comparator 7, a reference number 4 denotes a tuner section for selecting a desired carrier frequency, for amplifying the selected frequency, and for converting the amplified frequency into an Intermediate Frequency (IF). Reference number 5 designates a Phase Locked Loop (PLL) section for controlling the channel frequencies transmitted from broadcast stations received in the tuner section 4, reference number 6 denotes a Frequency Modulation (FM) detection section for converting the FM signal (sig4a) which has been converted with the Intermediate Frequency (IF) by the tuner section 4 into a base band signal (sig6a). The FM detection section 6 generates a stop signal (sig6b) to stop a scanning for a desired broadcast frequency during an automatic broadcast frequency selection operation and a received electric field intensity signal, namely a S meter signal (sig6b), which is a smoothed output of the intermediate frequency signal, and transmits the S meter signal (sig6b). The receive section in the conventional digital receiver shown in FIG. 40 includes the components 1 to 6 described above.
Reference number 8 denotes an analogue to digital (A/D) conversion device for the voltage value of the S meter signal (sig6b) to a digital signal in a digital form to transmit it to a control section 11. Reference number 7 designates a comparator for comparing the voltage of the S meter signal (sig6b) with a reference voltage VR1 and for transmitting a control signal (sig7a) as the comparison result of the comparison operation to the diversity section 3.
Reference number 9 denotes a digital demodulation section for selecting a multiplex transmission signal which is modulated in a digital form from the base band signal (sig6a) by the FM detection section 6, for digitally demodulating the multiplex transmission signal, and for generating a data signal (sig9a) and a synchronous clock signal (sig9b), reference number 10 designates an error correction section for performing an error correction operation based on an error correction flag in the multiplex transmission signal, and generating a data signal (sig10a) obtained after the error correction operation, and auxiliary information (sig10b) such as a synchronous establishment signal, a receive rate and the like. Reference number 11 designates the control section for performing tuning control and a data processing of received data from the error correction section 10, and for processing an operational signal as a control signal from an operation section 13 which is indicated by an operator. Reference number 12 designates a display section for displaying information based on data from the control section 11, and the reference number 13 is the operation section for receiving required data such as a tuning frequency which is selected by an operator and generating and transmitting the control data based on the selected tuning frequency and the like to the control section 11.
FIG. 41 is a drawing showing an example of an internal circuit of the digital demodulation section 9 in the conventional digital receiver shown in FIG. 40.
In the demodulation section 9 shown in FIG. 41, reference number 16 is a Band Pass Filter section for selecting the multiplex transmission signal which is modulated in a digital form in a base band signal transmitted from the FM detection section 6, reference number 17 is a binary quantization device for converting the digital modulated signal into a binary signal, reference number 18 is a delay device for delaying the binary signal (sig17) by the time period of 1 bit in order to perform a delay detection operation and generating a delayed signal (sig18), reference number 19 is an exclusive OR operation device for performing an exclusive OR operation between the binary signal (sig17) and the delayed signal (sig18), reference number 20 denotes a Low Pass Filter (LPF) for eliminating a high frequency component in the output of the exclusive OR operation device. Reference number 21 designates a data judgement device for judging of a state of the output signal from the LPF 20, and for converting this output signal into a digital wave-form and for transferring a judgement signal (sig9a) as the result of the judgement by the data judgement device 21 which is the data signal (sig9a) which is demodulated.
Reference number 23 designates a binary code quantization phase comparator for detecting a phase difference between the digital detection signal and the synchronous clock signal (sig9b) at a change point of the digital detection signal in value, and for generating a leading phase pulse (sig23a) and a delay phase pulse (sig23b). Reference number 24 denotes a sequential filter, which includes counter circuits capable of executing a digital integration operation, for performing an integration count operation to count output from the binary code quantization phase comparator 23 in order to eliminate an influence of a noise such as jitter, and for generating and transmitting a delay phase control signal (sig24a) and a leading phase control signal (sig24b). Reference number 25 denotes a fixed frequency oscillator, a reference number 26 designates a pulse addition/elimination device for adding a pulse to the output from the fixed frequency oscillator 25 when receiving the delay phase control signal (sig24a) from the sequential filter 24, and for eliminating the pulse when receiving the leading phase control signal (sig24b) from the sequential filter 24. A reference number 27 denotes a divider for dividing the output transmitted from the pulse addition/elimination device 26 into the synchronous clock signal (sig9b). Thus, a synchronous clock reproduction device 22 includes the components designated by the reference number 23-37 described above.
FIG. 42 is an example of an internal circuit of the diversity section 3 in the conventional digital receiver device shown in FIG. 40. In the diversity section 3 shown in FIG. 42, reference number 302 designates a selection device for selecting one of the output signal from the fixed frequency oscillator 301 and a ground signal based on the control signal (sig7a) from the comparator 7 and transmitting the selected one, reference number 303 designates a flip flop circuit for inverting a logical value of the current output signal from the flip flop circuit 303 when receiving a rising edge of the output signal from the selection device 302. Reference number 304 denotes a selection device for selecting one of the antennas 1 and 2 based on the output signal as a control signal from the flip flop circuit 303. Thus, the diversity section 3 includes the components designated by the reference numbers 301 to 304 described above.
Next, the operation of the diversity section 3 described above will now be explained.
Firstly, the diversity section 3 selects one of the antennas 1 and 2 based on the control signal from the comparator 7 which is also controlled based on the S meter signal (sig6b) from the FM detection section 6 and transmits a high frequency signal (sig3) which has received by the selected antenna. Because the selection device 302 in the diversity section 3 selects and transmits an output signal (sig3) from the fixed frequency oscillator 301 to the tuner section 4 when the output signal (sig7a) from the comparator 7 is a positive logical value where the voltage value of the S meter signal having the feature shown in FIG. 44 is not more than an antenna switch voltage level, the antennas 1 and 2 are switched alternately when the output signal (sig303) from the flip flop 303 is periodically changed to the positive logical value and a negative logical value. This antenna switching operation described above is continued until the control signal (sig7a) is changed to the negative logical value as the output signal from the comparator 7 until the voltage value of the S meter signal (sig6b) is more than the antenna switching level voltage and after the selection device 302 selects and transmits the ground signal, and after the output signal from the flip flop 303 is fixed in order to selects one of the antennas 1 and 2 continuously.
FIG. 43 shows an example of changing the value of the S meter signal (sig6a) and the antenna switch operation.
The tuner section 4 tunes the high frequency signal (sig3) from the diversity section 3 with a desired frequency based on the tuning voltage transmitted form the PLL section 5 and converts the desired high frequency signal in the high frequency signal (sig3) to the Intermediate Frequency signal.
The FM detection section 6 receives the Intermediate frequency signal from the tuner section 4 and performs an FM detection operation of the Intermediate frequency (IF) signal received and converts it in to a baseband signal (sig6b), and transmits the baseband signal (sig6b), the S meter signal which is obtained by rectification of the Intermediate Frequency (IF) signal, and the stop signal, indicating that the strength of the received electric magnetic field is more than a desired strength.
FIG. 43 shows an output characteristic of the stop signal to the received electric magnetic field in the conventional digital receiver shown in FIG. 40.
FIG. 44 shows an output characteristic of the S meter signal to the received electric magnetic field in the conventional digital receiver shown in FIG. 40.
The digital demodulation section 9 selects a multiplex transmission signal which is modulated in a digital form in the baseband signal (sig6a) transmitted from the FM detection section 6 and generates a digital demodulated signal (sig9a) and a synchronous clock signal (sig9b) which will be described later and transmits them.
An audio processing section 14 selects an audio signal in the baseband signal (sig6a) transmitted from the FM detection section 6 and amplifies an audio stereo signal obtained by demodulating the audio signal in stereo form and transmits the audio stereo signal to the speaker in order to drive the speaker 15.
The error correction section 10 receives the digital demodulated signal (sig9a) transmitted from the digital demodulation section 9 and performs the error correction operation for the digital demodulated signal (sig9a) by using the error correction flag in the digital demodulated signal (sig9a) and generates a data signal (sig10a) and the auxiliary information (sig10b) such as the synchronous establishing signal and the receive rate and transmits them to the control section 11.
The control section 11 receives the data signal (sig10a) from the error correction section 10 and displays the data signal (sig10a) on the display section 12 and performs several control operation such as the tuning control operation and the audio control operation.
Next, the tuning operation of the control section 11 in the conventional digital receiver shown in FIG. 40 will be explained. The tuning operation of the control section 11 relates to features of a digital receiver according to the present invention.
In the tuning control operation, the data (sig11b) indicating a tuning frequency is transmitted from the control section 11 to the PLL section 5 by using the PLL control signal (sig11b). Then the PLL section 5 generates the tuning voltage based on the data (sig11) indicating the tuning frequency. Then the tuner section 4 tunes the high frequency signal (sig3) from the diversity section 3 based on the tuning voltage.
A fully automatic selection operation for broadcast stations sequentially changes data of the tuning frequency and scans the tuning frequency and stops the scanning operation when the strength of the received electromagnetic field is more than the predetermined value by using the stop signal (sig6c) transmitted from the FM detection section 6.
Prior to explanation of the digital demodulation operation executed by the digital demodulation section 9, we will explain the basic theory about the delay detection method which is used in the conventional digital receiver shown in FIG. 40.
In general, a modulated signal is defined the following equation EQU s(t)=cos 2.pi.f t+.PHI.(t)!,
where f is a carrier frequency of a digital modulated signal, and .PHI.(t) is a digital modulated component.
When the modulated signal is multiplied by a signal which is delayed by the time period of a bit and then the high frequency component in the result of the multiplication is eliminated, the sig20 is EQU sig20=cos 2.pi.f t+.PHI.(t)-.PHI.(t-T!.
Because the term "2.pi. f t" becomes 9.5.pi. in a FM multiplex broadcasting, the above equation becomes EQU sig20=sin .PHI.(t)-.PHI.(t-T)!.
Thus, only modulated component .PHI. (t) in the modulated signal can be selected.
This digital modulation method used for the FM multiplex broadcasting is called the L-MSK modulation method.
This modulation method is one of the frequency modulation methods. In this modulation method, as shown in FIG. 45, the positive logical state is 80 KHz and the negative logical state is 72 KHz.
Next, the operation of the digital demodulation section 9 will be explained.
Because the baseband signal of the FM multiplex broadcasting has a spectrum structure as shown in FIG. 46, a multiplex transmission signal which is modulated in a digital form by the band-pass filter 16 is selected from the baseband signal (sig6a) transmitted from the FM detection section 6. Next, the digital modulated signal is converted into a digital signal by the binary code quantization device 17 in order to delay the digital modulated signal by the time period "T" of a bit by using the delay device including shift registers.
The exclusive OR logical output (sig19) between the digital modulated signal (sig17) which has been converted in a binary form and the signal (sig18) which is delayed by the time period "T" of a bit executed by the delay device 18 is transmitted to the data judgement device 21 through the LPF 20. Thereby the detection output signal in which a high frequency component is eliminated is obtained, as shown in FIG. 47.
The detection output signal (sig20) is judged by the data judgement device 21 in synchronization with the synchronous clock signal transmitted from the synchronous clock reproduction section 22 and the data judgement device generates the data signal (sig9a) based on the result of the data judgement operation.
The synchronous clock reproduction section 22 compares the detection output signal (sig20) with the synchronous clock signal at the rising edge or the falling edge of the detection output signal (sig20). Then, the section 22 generates the leading phase signal (sig23a) when the phase of the synchronous clock signal is ahead of the phase of the detection output signal, and generates the delay phase signal (sig23b) when the phase of the synchronous clock signal is delayed.
The sequential filter 24 in the synchronous clock reproduction section 22 includes counter circuits each of which has a function of the digital integration operation in order to decrease the influence of the noises such as jitter. Here the configuration and the operation of a typical N before M counter circuit will be explained.
The N before M counter circuit generates the delay phase control signal (sig24a) when the total number of the leading phase signals is N (where N is a positive number) and generates the leading phase control signal (sig24b) when the total number of the delay phase signals is N (where N is a positive number), until the total sum of the numbers of the leading phase signals and the delay phase signals reaches M (where M is a positive number). In addition, the N before M counter circuit is reset when the total number of the leading phase signals and the delay phase signal reaches M (where M is a positive number).
The pulse addition/elimination device 26 transmits the output from the oscillator 25 not including a pulse when the device 26 receives the delay control signal (sig24a) from the sequential filter 24. On the other hand, the pulse addition/elimination device 26 transmits the output from the oscillator 25 including a pulse when the device 26 receives the leading control signal (sig24b) from the sequential filter 24.
The divider 27 divides the signal from the pulse addition/elimination device 26 and generates the synchronous clock signal (sig9b). The oscillation frequency from the oscillator 25 is selected as to become a frequency that is k times of the frequency of the synchronous clock signal, and the divided rate of the divider 27 is selected as to become the 1/k of the oscillation frequency from the oscillator 25 (where k is a positive integer).
Japanese Laid-Open Patent Applications Nos. 6-276113, 4-47729, and 4-47730 discuss conventional digital receivers, such as the conventional FM multiplex broadcast receivers described above.
Since the conventional FM multiplex broadcast receiver has the configuration described above, there is no method to detect a data receiving state of the receiver other than the method wherein the data receiving state is detected by receiving the synchronous establishing signal (sig10b) to inform the establishment of the data synchronous operation for the data transmitted from the error correction section 10, or by using the data error rate obtained by the error detection operation or the error correction operation, or by using the S meter value.
There are a block synchronous establishing signal and a frame synchronous establishing signal in the synchronous establishing signal. In the use of the block synchronous establishing signal, there is a problem that there is a great time delay which is counted from the receiving of a electromagnetic wave transmitted from a broadcast station to the detection of the synchronous establishing signal because this block synchronous establishing signal is obtained based on a sequential detection of the synchronous bit by several times. Accordingly, it is difficult to use the block synchronous establishing signal as a control signal for devices such as the diversity section 3 shown in FIG. 40 where a rapid response is required.
FIG. 48 shows a data format structure used for the FM multiplex broadcasting. In the case of the FM multiplex broadcasting, since a block is made up of 272 bits, a time delay of several hundred m sec! is caused in order to detect the establishment of the block synchronous in some case. In addition, because 16 bits in a block is used for the establishment of the block synchronous operation, there is no reliability that the synchronous bits (16 bits) is equal to the other part of the data format in receiving state such as a receiving time, as shown in FIG. 48.
Further, because the frame synchronous establishment signal is generated after receiving of the synchronous bits having a predetermined pattern, it takes more time for detecting the establishment of the frame synchronous rather than that of the block synchronous. In addition, because the receiving rate is calculated based on the number of blocks which have been uncorrected in the error correction operation, it take more times to detect the establishment of the receiving rate rather than that of the frame synchronous establishment signal.
Although, the relationship between a voltage value of the S meter signal and the receiving rate, namely the error rate can be clearly shown by using the S meter signal (sig6b), it is difficult to detect a deterioration of the data receiving state which is caused by a phase difference of multi-path even if the DU rate is increased. Accordingly, in some cases, the data receiving state cannot be detected by using the S meter signal (sig6b).
In addition, all of FM broadcast stations do not always transmit a multiplexed broadcast. Further, all of actual broadcast time periods in a FM multiplex broadcast station do not transmit the multiplexed broadcast. Accordingly, it can not be detected whether or not the multiplexed broadcasting is now ON by using the S meter signal (sig6b) or the stop signal (sig6c). In this case, when automatically selects a multiplex broadcasting, it must be detect the absence of the multiplex broadcasting by using the synchronous establishment signal and the receiving rate after selecting it based on the S meter signal (sig6b) or the stop signal (sig6c). Further, in this case, it must be check the absence of the multiplex broadcasting for a broadcast station which transmits no multiplexed broadcast. Because it takes more times in the case described above, there is a problem.
In addition, there is information to display after accumulating received data in a memory in the conventional FM multiplexed broadcast described above. Therefore, in some cases the received data can not be displayed before the completion of data accumulation even if the data receiving state is good.
Because the conventional FM multiplex broadcast receiver has the configuration described above, it is inconvenient in the conventional receiver that an operator cannot immediately know whether received data will be displayed after the completion of the data accumulation in a good data receiving state or there is no data to display in a poor data receiving state.
Moreover, because the sequential filter 24 for reducing the influence of noises such as jitter by performing an integral count operation of the output from the binary code quantization phase comparator is used in the conventional clock synchronous reproduction section 22, it is difficult to respond to a sharp phase change which is caused in the diversity section 3 by switching the antennas 1 and 2. This is also a problem.